In order to increase the performance of semiconductor devices, the structures of transistors have been miniaturized. However, it is becoming difficult to improve the speeds of operation of transistors only by miniaturization of the structures of transistors because the minimum feature sizes (for example the minimum gate lengths) that are now required have reached the order of the wavelength of light and driving voltage decreases with decreasing feature size.
Under these circumstances, it has generally found that the mobility of electrons (or holes) in silicon crystals is changed by applying a strain to the silicon crystals. The property is being widely used to improve the speeds of operation of transistors. For example, the carrier mobility of field-effect transistors is improved by applying a strain to silicon crystals in channel regions by stress films formed on a silicon substrate (Patent Document 1).
Patent Document 1 discloses that two types of stress films covering field-effect transistors are formed, which apply tensile stress and compressive stress on the silicon substrate. The two types of stress films apply tensile stress to the channel region of an n-channel transistor and compressive stress to the channel region of a p-type transistor.
Patent Document 1: Japanese Patent Laid-Open No. 2005-57301
Today, stress films that apply tensile stress to channel regions are provided by depositing a material such as a silicon nitride and then exposing the silicon nitride to ultraviolet (UV) light, for example. When the film deposited by the process is shrunk, the following problem may occur.
FIGS. 12 to 15 are cross-sectional views of a stress film formed by a conventional method. FIG. 12 is a cross-sectional view of a silicon nitride film deposited on n-channel transistors 10a, 10b by Chemical Vapor Deposition (CVD). FIG. 13 is a cross-sectional view of the silicon nitride film shrunk by UV exposure. FIGS. 14 and 15 are cross-sectional views of regions where p-channel transistors 20a, 20b are formed.
A surface may be formed in the silicon nitride film 60a formed as described above in a region between adjacent gate electrodes 15a, 15b where the portions of silicon nitride film 60a grown from the sidewalls of the adjacent gate electrodes join together (the surface will be referred to as discontinuous surface hereinafter). When subsequently the silicon nitride film 60a is shrunk by UV exposure, the silicon nitride film 60 at the discontinuous surface may break as shown in FIG. 13. If the silicon nitride film 60 breaks, stress may not be applied to the transistors. Portion A of the silicon nitride film 60 that was continuous when the silicon nitride film 60 was deposited also breaks because an impact caused when the discontinuous surface 4 in FIG. 12 was separated was applied to portion A. The impact caused when the discontinuous surface 4 was separated may propagate to the silicon substrate and may cause cracks on the surface of Shallow Trench Isolations (STIs) 2, for example.
Usually p-channel transistors are also formed on the same semiconductor substrate. The hole mobility of a p-channel transistor decreases when a tensile stress is applied to its channel region. Therefore, an additional step of selectively removing the tensile stress film formed over the entire semiconductor substrate is required. FIGS. 14 and 15 are cross-sectional views of a region where p-channel transistors 20a, 20b are formed. The silicon nitride film 60a deposited has overhangs between adjacent gate electrodes 25a and 25b and a void is formed between the electrodes. In this case, little silicon nitride film 60a is formed in portion B and therefore the overhangs and portion B are etched faster during the process of etching the silicon nitride film 60 away as shown in FIG. 15. Consequently, the surface of the silicon substrate 1 is damaged during the subsequent etching.